Design and Implementation of High Resolution Digital Time Discrimination Module by High Speed ADC and FPGA (II)

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Project title

Code/計畫編號

NSC102-NU-E019-001-NU

Translated Name/計畫中文名

以高速ADC與FPGA設計並實現應用於PET之高解析數位時間鑑別技術(II)

Project Coordinator/計畫主持人

Tzong-Dar Wu

Funding Organization/主管機關

National Science and Technology Council

Department/Unit

Department of Electrical Engineering

Website

https://www.grb.gov.tw/search/planDetail?id=2862191

Year

2013

Start date/計畫起

01-01-2013

Expected Completion/計畫迄

01-12-2013

Bugetid/研究經費

487千元

ResearchField/研究領域

醫學技術
醫學工程

" 由於數位技術的演進，傳統 PET 電子系統中事件位置、能量、時間等資訊的獲得，逐漸由數位訊號處理替代。數位式訊號處理電路可在不改變硬體的情形下，僅透過軔體與軟體的修改即可更新產品版本或提升性能，具有成本低、高彈性、擴充性佳等特性。然而正子事件脈衝訊號上升時間極短，類比數位轉換器取樣到的資料並無法表示脈衝信號的全貌，因此在事件資訊的獲得中，精準事件時間的取得最具難度。若能提出有效的時間資訊演算法，提供準確的正子時間資訊及符合事件之計算，並提高 PET 事件時間解析度，對系統效能影響頗大。本計劃將藉由數位信號處理方式來實現應用於全數位正子斷層造影中的時間鑑別技術，而實現方法為利用線性擬合概念與浮點數運算等數值理論來計算出更精準的正子事件抵達時間，產生更為精確的時間標記，預期能有效大幅提升全數位正子斷層造影的系統時間平均解析度。本計劃將使用現有國外製造之高速 ADC 與 FPGA 整合模組板，設計適合於 FPGA 硬體的數位脈衝信號處理演算法，以得到最佳化的時間資訊。完成數位時間鑑別模組演算法設計之後將進行實際 PET 偵檢器模組 1 對 1 的實驗，了解整體系統之性能，藉由實驗結果修改 FPGA 電路設計與結構，得到快速且有效率之高解析度時間信號處理演算法。 " " With the evolution of the digital signal process techniques, the event position, energy, and timing information of the Position Emission Tomography (PET) are obtained more easily than that getting from the traditional PET technology. In addition, the digital PET system performance can be improved by the update of the firmware and software only. Without changing the hardware, the digital PET systems have the properties of low cost, high flexibility, and high expandability. Since the positron event of the PET has very short rise-time, the precise timing information is hard to be obtained. To improve the event time resolution in coincidence process, we need a high efficiency time discrimination algorithm for the digital signal process electronics. In this project, we propose the digital signal process technique to implement the time discrimination algorithm in the digital PET system. The linear interpolation methods and floating computation technique are used to realize the core of the algorithm in order to obtain the more precise timing information. It is expected that with the design of the proposed algorithm, the average resolution of the event time in the digital PET system can be improved. The high speed ADC and FPGA integrated module boards will be used in this project to develop the time discrimination algorithm suited for the FPGA electronics. After the design and implementation of the timing module, the timing experiments for 1 by 1 PET detectors will be carried out in order to find out the performance of the proposed timing module. To get the high speed and high efficiency time discrimination unit, the timing algorithm implemented in the FPGA will be modified by the experiment results. "

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Design and Implementation of High Resolution Digital Time Discrimination Module by High Speed ADC and FPGA (II)

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