http://scholars.ntou.edu.tw/handle/123456789/4847
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Dah-Jing Jwo | en_US |
dc.date.accessioned | 2020-11-19T03:03:40Z | - |
dc.date.available | 2020-11-19T03:03:40Z | - |
dc.date.issued | 2005-01 | - |
dc.identifier.issn | 0373-4633 | - |
dc.identifier.uri | http://scholars.ntou.edu.tw/handle/123456789/4847 | - |
dc.description.abstract | The solution for the receiver's position and clock bias using four or more GPS pseudorange measurements involve nonlinear quadratic equations. One of the popular techniques attempts to linearise the equations and solve them by the least-squares (LS) scheme based on an iterative gradient approach. For real-time applications when the solution is to be obtained within a time of the order of a hundred nanoseconds, a digital computer often cannot comply with the desired computation time, or its use is too expensive. In this paper, two ordinary differential equation formulation schemes and corresponding circuits of neuron-like analog processors will be employed for GPS navigation processing. The circuits of simple neuron-like analog processors are employed essentially for solving systems of linear equations based on the criterion of mean square error minimization, which is commonly utilized for determining positioning solutions in the GPS receivers. Experiments on single epoch and thereafter dynamic positioning will be conducted by computer simulation to validate the usefulness of the proposed scheme. The solutions will be assessed and compared to those provided by the conventional method in which pseudo-inverse matrix calculation by digital computer is involved. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Cambridge University Press | en_US |
dc.relation.ispartof | Journal of Navigation | en_US |
dc.subject | GPS | en_US |
dc.subject | Real-time Neurocomputing | en_US |
dc.subject | Neural Networks | en_US |
dc.subject | Analogue Processors | en_US |
dc.title | GPS navigation solutions by analogue neural network least-squares processors | en_US |
dc.type | journal article | en_US |
dc.identifier.doi | <Go to ISI>://WOS:000228383600008 | - |
dc.identifier.doi | <Go to ISI>://WOS:000228383600008 | - |
dc.identifier.doi | 10.1017/s0373463304003017 | - |
dc.identifier.doi | <Go to ISI>://WOS:000228383600008 | - |
dc.identifier.doi | <Go to ISI>://WOS:000228383600008 | - |
dc.identifier.url | <Go to ISI>://WOS:000228383600008 | |
dc.relation.journalvolume | 58 | en_US |
dc.relation.journalissue | 1 | en_US |
dc.relation.pages | 105 - 118 | en_US |
item.cerifentitytype | Publications | - |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
item.languageiso639-1 | en | - |
crisitem.author.dept | College of Electrical Engineering and Computer Science | - |
crisitem.author.dept | Department of Communications, Navigation and Control Engineering | - |
crisitem.author.dept | National Taiwan Ocean University,NTOU | - |
crisitem.author.parentorg | National Taiwan Ocean University,NTOU | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 通訊與導航工程學系 |
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