|Title:||High-Speed Searching of Optimum Switching Pattern for Digital Active Gate Drive to Adapt to Various Load Conditions||Authors:||Cheng, Yu Shan
|Keywords:||Logic gates;Switches;Surges;Optimization;Inverters;Legged locomotion;Linear programming;Active gate drive;full-bridge inverter;optimum driving patterns||Issue Date:||1-May-2022||Publisher:||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC||Journal Volume:||69||Journal Issue:||5||Start page/Pages:||5185-5194||Source:||IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS||Abstract:||
Digital active gate driving has been shown to effectively manage the switching performance for power devices with the adjustable driving waveforms. However, most of the studies are based on a dedicated test circuit rather than a practical inverter with the sinusoidal output current. In fact, it is the dependence on the load current that makes the design of the gate driving profiles a critical issue. To investigate the digital active gate driver in an inverter application, this article has applied optimal patterns adapting to time-varying output load current. Prior to the search of optimal patterns, the proper design of time slot is discussed with three different time resolutions. With the proper resolution determined for patterns, multiple optimizations are carried out for different current conditions. In this way, the search for optimal patterns can be completed in an efficient time. Next, a lookup table of optimal switching pattern in correspondence with each certain load current condition was built in advance. According to the output load current, the optimal pattern is selected based on the lookup table. Compared to conventional constant driving waveform, the power loss has been reduced by 7% with full optimal lookup table applied.
|Appears in Collections:||電機工程學系|
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