|Title:||Efficient Hardware Implementation of CORDIC-Based Symbol Detector for GSM MIMO Systems: Algorithm and Hardware Architecture||Authors:||Lu, Hoang-Yang
|Keywords:||Symbols;Detectors;MIMO communication;Hardware;GSM;Computer architecture;Transmitting antennas;Givens rotation;CORDIC;symbol detector;GSM MIMO||Issue Date:||1-Jan-2022||Publisher:||IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC||Journal Volume:||10||Start page/Pages:||114232-114241||Source:||IEEE ACCESS||Abstract:||
Aiming at providing an efficient hardware architecture for generalized spatial modulation (GSM) multiple-input multiple-output (MIMO) systems, in this paper a COordinate Rotation DIgital Computer (CORDIC) -based symbol detector is proposed. In the proposed detector, several CORDIC-based Givens rotation modules are conducted in parallel for the transmit antenna combinations (TACs) to facilitate QR-decomposition. After that, the proposed detector uses adders, shifters, and backward substitution mechanisms to currently estimate symbols for the corresponding TAC. At last, the estimated symbols and corresponding TAC index with the smallest distance measurement are chosen as the final solution. In particular, to achieve efficient hardware implementation, the architecture of the proposed detector has several features, including multiplication-free ranking mechanism, parallel CORDIC-based architectures, and shorter-bit-length multipliers. In addition, the overall architecture is pipelined to speed up the processing of the hardware. At last, computer simulations and hardware implementation are conducted under the configuration of four transmit, two active transmit, and four receive antennas. Simulation results reveal the proposed detector performs near to the optimal maximum likelihood (ML), but uses lower computational complexity. Additionally, the VLSI implementation results under the TSMC 90-nm CMOS technology show that the proposed hardware architecture requires 266K gates (KGEs), provides detection throughput 2.008 Gbps, works with pre-processing latency of 47 clock cycles, and has the hardware efficiency 7.54 (Mbps/KGEs) while operating at frequency 200.8 MHz. Moreover, implementation comparisons show the proposed architecture provides high throughput rate as well as hardware efficiency, and works with low pre-processing latency.
|Appears in Collections:||資訊工程學系|
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