第 1 到 64 筆結果，共 64 筆。
| 公開日期 | 標題 | 作者 | 來源出版物 | WOS | 全文 | |
|---|---|---|---|---|---|---|
| 1 | 2016 | 結合即時路況與共乘模式的大眾交通工具導引系統 | 馬永昌 ; 嚴茂旭 ; 賴瀅心 | |||
| 2 | 2014 | 利用Wi-Fi Direct輔助的即時交通路況系統 | 馬永昌 ; 嚴茂旭 ; 李奕親 | |||
| 3 | 2010 | Wavefront Architecture for Computing the Dynamic Space Warping Algorithm | Mao-Hsu Yen ; Yeong-Chang Maa ; Bing-Kun Chan; Wei-Heng Chen; Chih-Hao Ting | |||
| 4 | 2003 | VLSI Implementation of Polygonal FPGA design | Mao-Hsu Yen | |||
| 5 | 2017 | VLSI Implementation of PIC16f84 MCU with In-system Programming | Mao-Hsu Yen ; Wei-Jui Cheng; Chiu-Kuo Chen; Chia-Hung Su; Shih-Bin Lu; Yin-Cheng Chang; Da-Chiang Chang | |||
| 6 | 2015 | VLSI Implementation of FPGA Design using Water-Molecule-Shaped Switch Block | Mao-Hsu Yen ; Chih-Wei Lin ; Yeong-Chang Maa ; Hung-Kuan Yen; Pei-Jung Tsai | |||
| 7 | 2014 | VLSI Implementation of 8051 MCU with In-System Programming | Mao-Hsu Yen ; Yeong-Chang Maa ; Y-S Lin; George Lai; Shu-Ping Zheng | |||
| 8 | 2016 | VLSI Implementation of 8051 MCU with Decoupling Capacitor for IC-EMC | Mao-Hsu Yen ; Pei-Jung Tsai; Yeong-Chang Maa ; Chiu-Kuo Chen; Yen-Tang Chang | |||
| 9 | 2015 | VLSI Implementation of 8051 MCU for IC-EMC Testing Platform | Mao-Hsu Yen ; Chang-Hsien Chung; Wei-Chung Chen; Chiu-Kuo Chen; Yen-Tang Chang | |||
| 10 | 2008 | A VLSI Architecture for Computing the Dynamic Space Warping Algorithm | 吳俊龍; 徐嘉延; 黃宇祥; 嚴茂旭 ; 馬永昌 | |||
| 11 | 2014 | Using Wi-Fi Direct to Assist Real-Time Traffic Conditions Delivery | Yeong-Chang Maa ; Mao-Hsu Yen ; Yi-Chin Li; Ying-Shin La | |||
| 12 | 2008 | A Unified Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications | Chu Yu; Mao-Hsu Yen ; Pao-Ann Hsiung; Sao-Jie Chen | |||
| 13 | 2003 | Transmission Gates design for Low Power adders | S.C. Yi; C. F. Hsieh; Mao-Hsu Yen | |||
| 14 | 2006 | A Three-Stage Three-Sided Rearrangeable Switching Network for Interconnection Chip | Mao-Hsu Yen ; Yeong-Chang Maa ; Chin-Fa Hsieh; Shiuh-Chung Yi | |||
| 15 | 2002 | A Three-Sided Rearrangeable Switching Network for FPGA | Mao-Hsu Yen | |||
| 16 | 1999 | Symmetric and Programmable Multi-Chip Module for Rapid Prototyping System | Mao-Hsu Yen | |||
| 17 | 2013 | Spring gauge system by using R-radius corner detection | 嚴茂旭 ; 辛華昀 ; Chih-Cheng Lai | 0 | ||
| 18 | 2008 | SIMD-Wavefront Architecture for Computing the Dynamic Time Warping Algorithm | Mao-Hsu Yen ; Yeong-Chang Maa ; Chu Yu; Yi-Shan Chen; Yu-Hsiang Huang | |||
| 19 | 2016 | Semantic-Based Graph Data Anonymization for Big Data Analysis. | Shu-Ming Hsieh; Mao-Hsu Yen ; Li-Jen Kao | |||
| 20 | 2010 | A Rearrangeable Hierarchical Interconnection Structure for FPGA Routing Resource | Mao-Hsu Yen ; Bing-Kun Chan; Chun-Ran Huang; Chih-Hao Ting; Zheng-Yan Huang | |||
| 21 | 2009 | A Rearrangeable Binary Tree Switching Network for FPGA Routing Architecture | Mao-Hsu Yen ; B. K. Zhan; Y. S. Chen; J. L. Hou | |||
| 22 | 2004 | A Rearrangeable and Nonblocking Switching Network for FPIC | Mao-Hsu Yen | |||
| 23 | 2011 | R-radius Corner Detection by Using Circular Mask | 嚴茂旭 ; 馬永昌 ; 詹炳坤; 黃政諺; 林晏鈴 | |||
| 24 | 2016 | The Public Transit Navigation System Combined with Real-Time Road Conditions and Carpooling Platform | Yeong-Chang Maa ; Mao-Hsu Yen ; Ying-Shin Lai | |||
| 25 | 1999 | Polygonal Routing Network for FPGA/FPIC | Mao-Hsu Yen | |||
| 26 | 2004 | Polygonal FPGA Design | Mao-Hsu Yen ; H. R. Liao; S. C. Yi; S. H. Huang | |||
| 27 | 2009 | Parallel Implementation of Convolution Encoder for Software Defined Radio on DSP Architecture | J. C. Lin; C. Yu; Mao-Hsu Yen ; P. A. Hsiung; S. J. Chen; Y. H. Hu | |||
| 28 | 2012 | On the Variants of Tagged Geometric History Length Branch Predictors | Yeong-Chang Maa ; Mao-Hsu Yen | |||
| 29 | 2011 | A novel low-power 64-point pipelined FFT/IFFT processor for OFDM applications | Chu Yu; Yi-Ting Liao; Mao-Hsu Yen ; Pao-Ann Hsiung; Sao-Jie Chen | |||
| 30 | 2009 | A Novel Broadcast Paradigm in Supporting Power-Saving Mobile Stations | Haw-Yun Shin ; Mao-Hsu Yen | |||
| 31 | 2010 | A Memoryless Viterbi Decoder for OFDM Systems | Chu Yu; Chih-Jhen Chen; Mao-Hsu Yen ; Pao-Ann Hsiung; Sao-Jie Chen | |||
| 32 | 2011 | Low-Power Variable-length Pipeline FFT/IFFT Processor for OFDM-based Communication Systems | Chu Yu; Yi-Ting Liao; Chien-Hung Kuo; Mao-Hsu Yen ; Sao-Jie Chen | |||
| 33 | 2009 | Low-Error Fixed-Width Modified Booth Multipliers | Chu Yu; Cheng-Hang Sung; Meng-Hsueh Chiang; Mao-Hsu Yen ; Hwai-Tsu Hu | |||
| 34 | 2010 | Improving Power Saving for Filter-Based Branch Target Buffer | Yeong-Chang Maa ; Mao-Hsu Yen ; Chun-Hung Wang; Guan-Luen Lee; Xumin Guo | |||
| 35 | 2009 | An Improved Dynamic Space Warping Algorithm for 2D Image Recognition | Mao-Hsu Yen ; C. Y. Hsu; W. H. Chen; Z. C. Wu | |||
| 36 | 2019 | The Implementation of Time Delay Integrator on Image Sensor | Po-Yen Huang; Ling Jer; Mao-Hsu Yen ; Yuan-Xin Xiao | |||
| 37 | 2017 | Implementation of Chip-Level EMC Strategies in 0.18 µm CMOS Technology | Yin-Cheng Chang; Ping-Yi Wang; Shawn S. H. Hsu; Mao-Hsu Yen ; Yen-Tang Chang; Chiu-Kuo Chen; Ta-Yeh Lin; Da-Chiang Chang | |||
| 38 | 2018 | Implementation of Certified 150-O Voltage Probe for IEC 61967-4 Conducted Electromagnetic Emission Measurement | CHANG YIN-CHENG; LIN TA-YEH; WANG PING-YI; HSU Shawn S. H.; Mao-Hsu Yen ; CHANG DA-CHIANG | |||
| 39 | 2010 | Implement an SDR Platform by Using GNU Radio and USRP | Mao-Hsu Yen ; Chu Yu; Kuang-Yu Shie; Yu-Hsiang Huang; Jiun-Liang Lin | |||
| 40 | 2016 | IC-EMC測試平台之PIC MCU設計 | 嚴茂旭 ; 鄭暐叡; 林憶霞; 馬永昌 ; 彭博豪; 陳秋國 | |||
| 41 | 2013 | Hyper-Universal Switch Network for FPIC Design | Mao-Hsu Yen ; Chu Yu; Yih-Hsia Lin; Chang-Hsien Chung | |||
| 42 | 2012 | Hyper-Universal Ring Switch Box for FPGA Design | Mao-Hsu Yen ; Yeong-Chang Maa ; Yu Chu; Wen-Shine Liu; Lee-An Chu | |||
| 43 | 2010 | Hierarchical Decoder for Filter-Based Low-Power BTB | Yeong-Chang Maa ; Mao-Hsu Yen ; Chun-Hung Wang; Guan-Luen Lee; Xumin Guo | |||
| 44 | 2010 | Hedging Filter for Power Aware Branch Prediction | Yeong-Chang Maa ; Mao-Hsu Yen ; Shu-Ming Kuo; Guan-Luen Lee | |||
| 45 | 2011 | A Generic Three-Sided Rearrangeable Switching Network for FPGA Routing | Mao-Hsu Yen ; Hoang-Yang Lu ; Wen-Shine Liu; Chang-Tu Wu | |||
| 46 | 2006 | FPGA with Rapid RTR for Embedded Systems | Mao-Hsu Yen ; S. Y. Cheng; Y. H. Lin; H. Y. Shin | |||
| 47 | 2018 | FPGA Implementation of PIC16LF1826 MCU | Mao-Hsu Yen ; Bo-Hao Peng; Wei-Chung Chen; Liang-Yang Lin; Chia-Hung Su; Yih-Hsia Lin; Yin-Cheng Chang; Da-Chiang Chang | |||
| 48 | 2016 | Fast group detection schemes for massive MIMOs | Bo-Sing Chen; R.-Y. Huang; Hoang-Yang Lu ; Mao-Hsu Yen | |||
| 49 | 2010 | Evaluating and Improving Variable Length History Branch Predictors | Yeong-Chang Maa ; Mao-Hsu Yen ; Yu-Tang Wang | |||
| 50 | 2018 | EMS Characterization of LDO with On-chip Decaps by Using Direct RF Power Injection Method | Yin-Cheng Chang; Ping-Yi Wang; Hsu-Feng Hsiao; Ta-Yeh Lin; Shuohung Hsu; Mao-Hsu Yen ; MingShan Lin; Da-Chiang Chang | |||
| 51 | 2007 | A DTW VLSI Chip for Computing the DSW Algorithm | Mao-Hsu Yen ; Yeong-Chang Maa ; Yih-Hsia Lin; Shin-Yi Cheng; Chun-Lung Wu | |||
| 52 | 2019 | Discrete 1_ Probe by Using Flip-Chip IPD Resistor and Amplifier for Inspecting EMI of a Packaged IC | Yin-Cheng Chang; Ta-Yeh Lin; Chaoping Hsieh; Shawn S. H. Hsu; Mao-Hsu Yen ; Jian-Li Dong; Da-Chiang Chang | |||
| 53 | 2015 | Design of the Multifunction IC-EMC Test Board with Off-Board Probes for Evaluating a Microcontroller | Yin-Cheng Chang; Ping-Yi Wang; Shuohung Hsu; Mao-Hsu Yen ; Yen-Tang Chang; Chiu-kuo Chen; Da-Chiang Chang | |||
| 54 | 2016 | The Design of Current Probe in the IEC Conducted Emission Measurement above 1 GHz | Yin-Cheng Chang; Ta-Yeh Lin; Ping-Yi Wang; Shawn S. H. Hsu; Mao-Hsu Yen ; Yen-Tang Chang; Ming-Shan Lin; Da-Chiang Chang | |||
| 55 | 2014 | Design of a New Hyperuniversal Switch Block for FPGA Chip | Mao-Hsu Yen ; Hung-Kuan Yen; Yeong-Chang Maa ; Ming-Yang Xu; Shu-Ping Zheng | |||
| 56 | 2011 | Design of a Low-Power OFDM Baseband Receiver for Wireless Communications | Chu Yu; Chien-Hung Kuo; Cheng-Hang Sung; Mao-Hsu Yen ; Sao-Jie Chen | |||
| 57 | 2010 | Design of a Low Power Viterbi Decoder for Wireless Communication Applications | Chih-Jhen Chen; Chu Yu; Mao-Hsu Yen ; Pao-Ann Hsiung; Sao-Jie Chen | |||
| 58 | 2009 | Design of a High-Speed Block Interleaving/Deinterleaving Architecture for Wireless Communication Applications | Chu Yu; Mao-Hsu Yen ; Pao-Ann Hsiung; Sao-Jie Chen | |||
| 59 | 2011 | Design and Analysis of Multipath Oriented Branch Predictors | Yeong-Chang Maa ; Mao-Hsu Yen | |||
| 60 | 2010 | Cost-Effective Branch Prediction by Combining Hedging and Filtering | Yeong-Chang Maa ; Mao-Hsu Yen ; Shu-Ming Kuo; Guan-Luen Lee | |||
| 61 | 2015 | Comparison between Routabilities of State-of-the-art Designs of Switch Blocks in FPGA | Mao-Hsu Yen ; Huang-Kuang Yen; Yih-Hsia Lin; Pei-Ting Huang; Pei-Jung Tsai | |||
| 62 | 2010 | ARAL-CR: An Adaptive Reasoning And Learning Cognitive Radio Platform | Sao-Jie Chen; Pao-Ann Hsiung; Chu Yu; Mao-Hsu Yen ; Sakir Sezer; Michael J. Schulte; Yu Hen Hu | |||
| 63 | 2010 | An Adaptive PID Controller | Jen-Yang Chen; Chuan-Hsi Liu; Haw-Yun Shin ; Mao-Hsu Yen | |||
| 64 | 2009 | A 900 MHz to 5.2 GHz Dual-Loop Feedback Multi-band LNA | J. W. Lin; D. T. Yen; W. Y. Hu; C. Yu; Mao-Hsu Yen ; P. A. Hsiung; S. J. Chen |
