A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller

Please use this identifier to cite or link to this item: http://scholars.ntou.edu.tw/handle/123456789/6986

Title:	A low-power, area-efficient all-digital delay-locked loop for DDR3 SDRAM controller
Authors:	Hong-Ming Chen Ma, S. Wang, L. Zhang, H. Pan, K. Y. Cheng, Y. H.
Issue Date:	Dec-2014
Journal Volume:	57
Journal Issue:	12
Source:	Science China-Information Sciences
URI:	http://scholars.ntou.edu.tw/handle/123456789/6986
ISSN:	1674-733X
DOI:	10.1007/s11432-014-5226-1 ://WOS:000346238500020
Appears in Collections:	水產養殖學系

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